A Phase-Locked Loop (PLL) is one type of clock circuit that compares input and output clock signals and attempts to create the output clock signal so that the output clock signal is aligned with the input clock signal. Alignment means that an edge of the output clock signal occurs at about the same time (e.g., within a small error) from an edge of the input clock signal. Generally, rising edges are used so that a rising edge of the output clock signal occurs at about the same time as a rising edge of the input clock signal. Typical PLLs comprise a phase comparator, low pass filter, and Voltage Controlled Oscillator (VCO). The phase comparator compares the input and output clock signals and produces an output that is related to a comparison between the input and output clock signals. For example, in a digital PLL, a phase comparator might produce an output proportional to a time difference between edges of the input and output clock signals. In an analog PLL, by contrast, a phase comparator might produce an output determined by an analog multiplication of the input and output clock signals. The filter acts to smooth the output of the phase comparator, and the VCO oscillates at a rate proportional to the voltage applied to the VCO from an output of the filter.
PLLs are used in a wide variety of situations, such as clock recovery from encoded digital streams, synchronization of clock signals, synchronization of input and output data, and locking onto a signal such as a radio signal. While PLLs are widely used, some problems with PLLs exist. For instance, conventional PLLs typically have some static phase error. This static phase error means that the edges of the input and output clock signals will never be exactly aligned. Moreover, PLLs typically do not provide variable phase shift capability. Instead, aside from the static phase error, the input and output clock signals are aligned (e.g., a phase shift of zero). Additionally, the PLLs have a loop noise bandwidth, which describes the effective bandwidth of the input clock signal. Noise and signal components outside the loop noise bandwidth are attenuated. Furthermore, conventional PLLs can take a large area on a semiconductor, can use quite a large amount of power, and contain variables that can be process, temperature, and voltage sensitive.
A need therefore exists for circuits that can use an input clock signal as a reference to provide an output clock signal and that can also provide variable phase shift, relative to the input clock signal, of the output clock signal.